This invention relates to the fabrication of semiconductor integrated circuits (ICs). More particularly, the present invention relates to improved methods and apparatus for etching an oxide layer in a plasma processing chamber.
In semiconductor IC fabrication, devices such as component transistors may be formed on a semiconductor wafer or substrate, which is typically made of silicon. Above the wafer, there may be disposed a plurality of layers from which the devices may be fabricated. Openings such as contacts and vias are etched in an oxide layer, which may be doped or undoped silicon oxide, pure silicon dioxide or silicates doped with boron, phosphorus, arsenic, or the like. Some types of oxides commonly used in the industry include, by way of example, tetra ethyl oxysilane (TEOS), boro-phosphosilicate glass (BPSG), spin-on glass (SOG), and phosphosilicate glass (PSG). The oxide layer can overlie a conductive or semiconductive layer such as polycrystalline silicon, metals such as aluminum, copper, titanium, tungsten, or alloys thereof, nitrides such as titanium nitride, or metal silicides such as titanium silicide, cobalt silicide, tungsten silicide, etc. To facilitate this discussion, FIG. 1 illustrates a cross-sectional view of a layer stack 100, representing the layers of an exemplar semiconductor IC. In the discussions that follow, it should be noted that other additional layers above, below, or between the layers shown may be present. Further, not all of the shown layers need necessarily be present and some or all may be substituted by other different layers.
At the bottom of layer stack 100, there is shown a wafer 102, which may be made of silicon or metal silicide. A metal layer 104 may be formed above wafer 102. An oxide layer 106, typically comprising SiO.sub.2, may be formed above metal layer 104. An overlaying photoresist (PR) layer 108, may then be formed atop oxide layer 106. Photoresist layer 108 represents a layer of conventional photoresist material, which may be patterned for etching, e.g., through exposure to ultra-violet rays. The layers of layer stack 100 are only exemplary and are readily recognizable to those skilled in the art and may be formed using any of a number of suitable and known deposition processes, including chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and physical vapor deposition (PVD) such as sputtering.
To form openings in the oxide layer, a portion of oxide layer 106 is etched using a suitable photoresist technique. By way of example, one such photoresist technique involves the patterning of photoresist layer 108 by exposing the photoresist material in a contact or stepper lithography system, and the development of the photoresist material to form a mask to facilitate subsequent etching. Using appropriate etchants, the areas of the oxide layer that are unprotected by the mask may then be etched away, leaving behind openings which may then be filled with metal to form the interconnect lines. For illustration purposes, FIG. 2 shows a cross-sectional view of layer stack 100 of FIG. 1 having an opening 110 in oxide layer 106 after conventional etching is completed.
To achieve greater circuit density, modern IC circuits are scaled with increasingly narrower design rules. As a result, the feature sizes, i.e., the width of the interconnect lines or the spacings (e.g., trenches) between adjacent openings, have steadily decreased, thus giving rise to the need to etch narrower and deeper openings. By way of example, while an opening diameter of approximately 0.8 microns (.mu.m) may be considered acceptable in a 4 megabit (Mb) dynamic random access memory (DRAM) IC, 256 Mb DRAM IC's preferably employ openings of higher aspect ratios with widths as small as 0.25 microns or even smaller.
With reference to FIG. 3, faceting of the photoresist 302 (as shown by facets 304) while etching the oxide layer 306 may cause the upper region of opening 308 to have a larger cross-sectional dimension than the cross-sectional dimension of the bottom region of opening 308. This loss of critical dimension control may be observed with aspect ratios as low as 3:1. The degradation in the desired vertical sidewall profile may be better understood with reference to FIG. 4.
FIG. 4 illustrates a cross-sectional view of a layer stack 400 having oxide layer 402 overlying a silicon substrate 404. A patterned photoresist layer 406 overlies oxide layer 402. A deep and narrow opening 408 (e.g., having an aspect ratio of 5:1 or greater) is etched in to oxide layer 402 using the prior art gas chemistry, which results in bowed sidewalls 410 due to lower passivation of the sidewalls relative to the passivation that takes place at the bottom of the opening. Adding more fluorocarbon to the etching gas chemistry could increase the passivation somewhat, but would also cause an etch stop to occur in oxide layer 402. The presence of bowed sidewalls 410 makes it difficult to fill opening 408 with metal to form an electrically sound contact since the top portion of the opening, having a smaller cross-section than the lower part due to the bowed sidewalls, will pinch off before the lower portion is entirely filled with metal, thus causing a void in the contact.
It should be appreciated by those skilled in the art that both loss of critical dimension control and the bowing sidewalls are undesired as either of these two characteristics may result in problems with maintaining substantially straight vertical profiles as well as correct sizing for the etched openings. In view of the foregoing, there are desired improved techniques of etching deep and narrow openings in an oxide layer.